On Tue, Mar 26, 2024 at 06:19:38PM +1100, Michael Ellerman wrote: > Mathieu Desnoyers <mathieu.desnoy...@efficios.com> writes: > The ISA doesn't specify the cache line size, other than it is smaller > than a page.
It also says it is "aligned". Nowhere is it said what an aligned size is, but it seems clear it has to be a power of two. > In practice all the 64-bit IBM server CPUs I'm aware of have used 128 > bytes. Yup. It is 128B on p3 already. > It is possible to discover at runtime via AUXV headers. But that's no > use if you want a compile-time constant. The architecture does not require the data block size to be equal to the instruction block size, already. But many programs subscribe to an overly simplified worldview, which is a big reason everything is 128B on all modern PowerPC. It is quite a nice tradeoff size, there has to be a huge change in the world for this to ever change :-) Segher
