Mathieu Desnoyers <mathieu.desnoy...@efficios.com> writes: > Hi, Hi Mathieu,
> In the powerpc architecture support within the liburcu project [1] > we have a cache line size defined as 256 bytes with the following > comment: > > /* Include size of POWER5+ L3 cache lines: 256 bytes */ > #define CAA_CACHE_LINE_SIZE 256 > > I recently received a pull request on github [2] asking to > change this to 128 bytes. All the material provided supports > that the cache line sizes on powerpc are 128 bytes or less (even > L3 on POWER7, POWER8, and POWER9) [3]. > > I wonder where the 256 bytes L3 cache line size for POWER5+ > we have in liburcu comes from, and I wonder if it's the right choice > for a cache line size on all powerpc, considering that the Linux > kernel cache line size appear to use 128 bytes on recent Power > architectures. I recall some benchmark experiments Paul and I did > on a 64-core 1.9GHz POWER5+ machine that benefited from a 256 bytes > cache line size, and I suppose this is why we came up with this > value, but I don't have the detailed specs of that machine. > > Any feedback on this matter would be appreciated. The ISA doesn't specify the cache line size, other than it is smaller than a page. In practice all the 64-bit IBM server CPUs I'm aware of have used 128 bytes. There are some 64-bit CPUs that use 64 bytes, eg. pasemi PA6T and Freescale e6500. It is possible to discover at runtime via AUXV headers. But that's no use if you want a compile-time constant. I'm happy to run some benchmarks if you can point me at what to run. I had a poke around the repository and found short_bench, but it seemed to run for a very long time. cheers
