> You are correct, the patch is wrong because it fails to account for IO > accesses.
Okay, I looked at the PowerPC ISA and found: "The memory barrier provides an ordering function for the storage accesses caused by Load, Store,and dcbz instructions that are executed by the processor executing the sync instruction and for which the specified storage location is in storage that is Memory Coherence Required and is neitherWrite Through Required nor Caching Inhibited.The applicable pairs are all pairs ai ,bj of such accesses except those in which ai is an accesscaused by a Store or dcbz instruction and bj is anaccess caused by a Load instruction." Thanks for your time, Michael. Sorry for the noise. > > Kautuk, I'm not sure what motivated you to look at these barriers, was > it just the documentation you linked to? I read the basic documentation. Now that I have access to the PowerISA document I guess I'll go through it more thoroughly. >
