On Wed, 9 Jul 2008 10:23:08 -0400 Josh Boyer <[EMAIL PROTECTED]> wrote:
> On Tue, 08 Jul 2008 15:54:40 +1000 > Benjamin Herrenschmidt <[EMAIL PROTECTED]> wrote: > > > This is some preliminary work to improve TLB management on SW loaded > > TLB powerpc platforms. This introduce support for non-atomic PTE > > operations in pgtable-ppc32.h and removes write back to the PTE from > > the TLB miss handlers. In addition, the DSI interrupt code no longer > > tries to fixup write permission, this is left to generic code, and > > _PAGE_HWWRITE is gone. > > > > Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]> > > Boots for me now. So far it's surviving a dbench run, and I'll try > hackbench/kernbench shortly. For those interested, here are the results of my stupidly simple hackbench runs: Setup: - AMCC PowerPC Sequoia 440EPx board, 128MiB of DRAM, 533 MHz CPU clock - NFS rootfs over 100MBit ethernet - soft-float userspace Times were gathered by booting to a prompt, running five 'hackbench 50' tests, and averaging the results. sequoia_defconfig: Avg time - 48.1118 seconds sequoia_defconfig+patch: Avg time - 47.8996 seconds I consider that difference to be in the noise range, but the important thing is that it doesn't show a regression in performance. Feel free to flame away at my lame testing. I didn't have the setup or time to do much else at the moment. josh _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
