On Jul 8, 2008, at 12:54 AM, Benjamin Herrenschmidt wrote:
This is some preliminary work to improve TLB management on SW loaded TLB powerpc platforms. This introduce support for non-atomic PTE operations in pgtable-ppc32.h and removes write back to the PTE from the TLB miss handlers. In addition, the DSI interrupt code no longer tries to fixup write permission, this is left to generic code, and _PAGE_HWWRITE is gone. Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]> --- This is a first step, plan is to do the same for FSL BookE, 405 and possibly 8xx too. From there, I want to rework a bit the execute permission handling to avoid multiple faults, add support for _PAGE_EXEC (no executable mappings), for prefaulting (especially for kmap) and proper SMP support for future SMP capable BookE platforms. v2. This version fixes a couple of typos, add a few comments and change use of flush_instruction_cache() to flush_icache_range() which will be more appropriate if there is ever an SMP variant. v3. Relying on the generic code to fixup _PAGE_ACCESSED doesn't work for exec faults because our cache coherency code in do_page_fault() will never go all the way to the generic code for these. We fix it up by always setting _PAGE_ACCESSED when setting _PAGE_HWEXEC in there. This version of the patch is rebased on top of -next
shouldn't you remove _PAGE_HWWRITE from 40x? (I'm still seeing it in pgtable-ppc32.h and head_40x.S)
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