in patch da414bb923d9 (Add FSL Qoriq DPAA FMan support to the SoC
device tree(s)) we added aliases for all ethernet ports, and linked
them to specific hardware devices, but we put them in the pre.dtsi
include file meaning any board wishing to use this file is stuck with
this port layout, even if it don't match the boards hardware. The Cyrus
5020 and 5040 boards are examples, they are based on the p5020 ref
design, but only have 2 ethernet ports.
Fix the problem by moving the ethernet aliases to the boards dts file
where we define the phy aliases.
Signed-off-by: Darren Stevens <dar...@stevens-zone.net>
---
Only patched the p5020ds and p5040ds as they are the boards I work
with. Others may need looking at.
arch/powerpc/boot/dts/fsl/p5020ds.dts | 7 +++++++
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 6 ------
arch/powerpc/boot/dts/fsl/p5040ds.dts | 13 +++++++++++++
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 12 ------------
4 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/p5020ds.dts
b/arch/powerpc/boot/dts/fsl/p5020ds.dts index b24adf9..cdf0559 100644
--- a/arch/powerpc/boot/dts/fsl/p5020ds.dts
+++ b/arch/powerpc/boot/dts/fsl/p5020ds.dts
@@ -53,6 +53,13 @@
emi1_rgmii = &hydra_mdio_rgmii;
emi1_sgmii = &hydra_mdio_sgmii;
emi2_xgmii = &hydra_mdio_xgmii;
+
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ ethernet5 = &enet5;
};
memory {
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi index 2d74ea8..8bc7a75
100644 --- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -81,12 +81,6 @@
raideng_jr3 = &raideng_jr3;
fman0 = &fman0;
- ethernet0 = &enet0;
- ethernet1 = &enet1;
- ethernet2 = &enet2;
- ethernet3 = &enet3;
- ethernet4 = &enet4;
- ethernet5 = &enet5;
};
cpus {
diff --git a/arch/powerpc/boot/dts/fsl/p5040ds.dts
b/arch/powerpc/boot/dts/fsl/p5040ds.dts index 30850b3..bffbba5 100644
--- a/arch/powerpc/boot/dts/fsl/p5040ds.dts
+++ b/arch/powerpc/boot/dts/fsl/p5040ds.dts
@@ -65,6 +65,19 @@
hydra_sg_slot6 = &hydra_sg_slot6;
hydra_xg_slot1 = &hydra_xg_slot1;
hydra_xg_slot2 = &hydra_xg_slot2;
+
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ ethernet5 = &enet5;
+ ethernet6 = &enet6;
+ ethernet7 = &enet7;
+ ethernet8 = &enet8;
+ ethernet9 = &enet9;
+ ethernet10 = &enet10;
+ ethernet11 = &enet11;
};
memory {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi index ed89dbb..bc4e0bc
100644 --- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -81,18 +81,6 @@
fman0 = &fman0;
fman1 = &fman1;
- ethernet0 = &enet0;
- ethernet1 = &enet1;
- ethernet2 = &enet2;
- ethernet3 = &enet3;
- ethernet4 = &enet4;
- ethernet5 = &enet5;
- ethernet6 = &enet6;
- ethernet7 = &enet7;
- ethernet8 = &enet8;
- ethernet9 = &enet9;
- ethernet10 = &enet10;
- ethernet11 = &enet11;
};
cpus {
