On 06/04/2020 13:07, Oliver O'Halloran wrote:
> Move it in with the rest of the TCE wrangling rather than carting around
> a static prototype in pci-ioda.c
>
> Signed-off-by: Oliver O'Halloran <ooh...@gmail.com>
Reviewed-by: Alexey Kardashevskiy <a...@ozlabs.ru>
> ---
> arch/powerpc/platforms/powernv/pci-ioda-tce.c | 28 +++++++++++++++++
> arch/powerpc/platforms/powernv/pci-ioda.c | 30 -------------------
> arch/powerpc/platforms/powernv/pci.h | 2 ++
> 3 files changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/arch/powerpc/platforms/powernv/pci-ioda-tce.c
> b/arch/powerpc/platforms/powernv/pci-ioda-tce.c
> index 5dc6847d5f4c..f923359d8afc 100644
> --- a/arch/powerpc/platforms/powernv/pci-ioda-tce.c
> +++ b/arch/powerpc/platforms/powernv/pci-ioda-tce.c
> @@ -17,6 +17,34 @@
> #include <asm/tce.h>
> #include "pci.h"
>
> +unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
> +{
> + struct pci_controller *hose = phb->hose;
> + struct device_node *dn = hose->dn;
> + unsigned long mask = 0;
> + int i, rc, count;
> + u32 val;
> +
> + count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
> + if (count <= 0) {
> + mask = SZ_4K | SZ_64K;
> + /* Add 16M for POWER8 by default */
> + if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
> + !cpu_has_feature(CPU_FTR_ARCH_300))
> + mask |= SZ_16M | SZ_256M;
> + return mask;
> + }
> +
> + for (i = 0; i < count; i++) {
> + rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
> + i, &val);
> + if (rc == 0)
> + mask |= 1ULL << val;
> + }
> +
> + return mask;
> +}
> +
> void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
> void *tce_mem, u64 tce_size,
> u64 dma_offset, unsigned int page_shift)
> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
> b/arch/powerpc/platforms/powernv/pci-ioda.c
> index 8b45b8e561e9..c020ade3a846 100644
> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
> @@ -2585,8 +2585,6 @@ static struct iommu_table_group_ops pnv_pci_ioda2_ops =
> {
> .release_ownership = pnv_ioda2_release_ownership,
> };
>
> -static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
> -
> static void pnv_pci_ioda_setup_iommu_api(void)
> {
> struct pci_controller *hose;
> @@ -2638,34 +2636,6 @@ static void pnv_pci_ioda_setup_iommu_api(void)
> static void pnv_pci_ioda_setup_iommu_api(void) { };
> #endif
>
> -static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
> -{
> - struct pci_controller *hose = phb->hose;
> - struct device_node *dn = hose->dn;
> - unsigned long mask = 0;
> - int i, rc, count;
> - u32 val;
> -
> - count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
> - if (count <= 0) {
> - mask = SZ_4K | SZ_64K;
> - /* Add 16M for POWER8 by default */
> - if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
> - !cpu_has_feature(CPU_FTR_ARCH_300))
> - mask |= SZ_16M | SZ_256M;
> - return mask;
> - }
> -
> - for (i = 0; i < count; i++) {
> - rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
> - i, &val);
> - if (rc == 0)
> - mask |= 1ULL << val;
> - }
> -
> - return mask;
> -}
> -
> static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
> struct pnv_ioda_pe *pe)
> {
> diff --git a/arch/powerpc/platforms/powernv/pci.h
> b/arch/powerpc/platforms/powernv/pci.h
> index d3bbdeab3a32..0c5845a1f05d 100644
> --- a/arch/powerpc/platforms/powernv/pci.h
> +++ b/arch/powerpc/platforms/powernv/pci.h
> @@ -244,4 +244,6 @@ extern void pnv_pci_setup_iommu_table(struct iommu_table
> *tbl,
> void *tce_mem, u64 tce_size,
> u64 dma_offset, unsigned int page_shift);
>
> +extern unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
> +
> #endif /* __POWERNV_PCI_H */
>
--
Alexey
