Hi Arndt，
-----Original Message-----
From: Arnd Bergmann <a...@arndb.de>
Sent: 2019年5月17日 16:59
To: Xiaowei Bao <xiaowei....@nxp.com>
Cc: Bjorn Helgaas <bhelg...@google.com>; Rob Herring <robh...@kernel.org>; Mark
Rutland <mark.rutl...@arm.com>; Shawn Guo <shawn...@kernel.org>; Leo Li
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<minghuan.l...@nxp.com>; Mingkai Hu <mingkai...@nxp.com>; Roy Zang
<roy.z...@nxp.com>; Kate Stewart <kstew...@linuxfoundation.org>; Philippe
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linux-pci <linux-...@vger.kernel.org>; DTML <devicet...@vger.kernel.org>; Linux
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Subject: Re: [EXT] Re: [PATCH 2/3] arm64: dts: ls1028a: Add PCIe controller DT
nodes
Caution: EXT Email
On Fri, May 17, 2019 at 5:21 AM Xiaowei Bao <xiaowei....@nxp.com> wrote:
> -----Original Message-----
> From: Arnd Bergmann <a...@arndb.de>
> On Wed, May 15, 2019 at 9:36 AM Xiaowei Bao <xiaowei....@nxp.com> wrote:
> > Signed-off-by: Xiaowei Bao <xiaowei....@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 52
> > ++++++++++++++++++++++++
> > 1 files changed, 52 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index b045812..50b579b 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -398,6 +398,58 @@
> > status = "disabled";
> > };
> >
> > + pcie@3400000 {
> > + compatible = "fsl,ls1028a-pcie";
> > + reg = <0x00 0x03400000 0x0 0x00100000 /*
> > controller registers */
> > + 0x80 0x00000000 0x0 0x00002000>; /*
> > configuration space */
> > + reg-names = "regs", "config";
> > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /*
> > PME interrupt */
> > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /*
> > aer interrupt */
> > + interrupt-names = "pme", "aer";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + dma-coherent;
> > + num-lanes = <4>;
> > + bus-range = <0x0 0xff>;
> > + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000
> > 0x0 0x00010000 /* downstream I/O */
> > + 0x82000000 0x0 0x40000000 0x80
> > + 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
>
> Are you sure there is no support for 64-bit BARs or prefetchable memory?
> [Xiaowei Bao] sorry for late reply, Thought that our Layerscape platform has
> not added prefetchable memory support in DTS, so this platform has not been
> added, I will submit a separate patch to add prefetchable memory support for
> all Layerscape platforms.
Ok, thanks.
> Of course, the prefetchable PCIE device can work in our boards,
> because the RC will assign non-prefetchable memory for this device. We
> reserve 1G no-prefetchable memory for PCIE device, it is enough for general
> devices.
Sure, many devices work just fine, this is mostly a question of supporting
those devices that do require multiple gigabytes, or that need prefetchable
memory semantics to get the expected performance. GPUs are the obvious example,
but I think there are others (infiniband?).
[Xiaowei Bao] sorry, I don't know much about infiniband and GPU, as you said, I
think many devices works fine with this DTS, I will add the prefetchable memory
entry in DTS future and submit another patch.
Arnd
