Frankly, the more I read the more perplexed I get. For example, according to BOOK III-S, chapter 3, the MSR bits are differ from the ones described in arch/powerpc/include/asm/reg.h. Bit zero, is LE, but in the book it is 64-bit mode.
Would someone be kind to explain what I do not understand? Thank you On Wed, Oct 3, 2018 at 7:07 AM Michael Ellerman <[email protected]> wrote: > > Raz <[email protected]> writes: > > > Hello > > > > I want to learn about powerpc architecture, mainly hypervisor and > > partioning. I download the books (1,2, and 3 ) but I feel it lacks > > a lot of information. Are there other books ? > > The ISA describes how the CPU works to allow you to implement a > hypervisor, but it doesn't describe any of the HV/Kernel APIs. > > That's mostly covered in "LoPAPR": > > https://members.openpowerfoundation.org/document/dl/469 > > > Although that's not been updated for Power9. > > cheers
