On Fri, 22 Feb 2008 22:15:58 +0300 Valentine Barshak <[EMAIL PROTECTED]> wrote:
> Benjamin Herrenschmidt wrote: > > On Thu, 2008-02-21 at 17:46 +0300, Valentine Barshak wrote: > >> The PowerPC 440GX Taishan board fails to reset EMAC3 (reset timeout error) > >> and because of that it can't find PHY chip. The older ibm_emac driver had > >> a workaround for that: the EMAC_CLK_INTERNAL/EMAC_CLK_EXTERNAL macros which > >> toggle the Ethernet Clock Select bit in the SDR0_MFR register. This patch > >> does the same for "ibm,emac-440gx" compatible chips. > > > > The main problem is that will force clock on -all- EMACs ... which can > > be a problem as they can be in probe at the same time. Might be worth > > also adding a global mutex around that block. > > I've tried to move clock selection inside the global emac_phy_map_lock > block. That works fine for 440GX. > > > > > Also, would you mind having a look at the other workaround for the > > similar bug? > > OK, I'll add 440EP/440GR workaround, but I'm not sure if we need it for > the currently supported boards. The older ibm_emac driver also has a > workaround for it on 405ep. This part uses CPC0 dcr registers. So, looks > like we'll have to search device tree for the CPC0 entry in ibm_newemac > driver, map dcr registers and select clock with dcr_read/write calls. > I've omitted the 405ep part, since there's currently no board supported. I'll be doing a 405EP port for .26. josh _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
