Hi Valentin,

This patch you added make the compiling issue on armv8.
Could you send another patch to resolve it?

CC      drivers/soc/samsung/pm_domains.o
  CC      drivers/soc/sunxi/sunxi_sram.o
  CC      drivers/soc/renesas/rcar-rst.o
  CC      drivers/soc/fsl/qe/qe_io.o
drivers/soc/fsl/qe/qe.c: In function 'qe_setbrg':
drivers/soc/fsl/qe/qe.c:248:2: error: implicit declaration of function 
'pvr_version_is' [-Werror=implicit-function-declaration]
  if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
  ^
  CC      drivers/soc/fsl/qe/ucc.o
  CC      drivers/soc/renesas/rcar-sysc.o
  CHK     kernel/config_data.h
cc1: some warnings being treated as errors
  CC      drivers/soc/tegra/fuse/fuse-tegra.o
  LD      drivers/soc/rockchip/built-in.o
  CC      drivers/soc/tegra/fuse/fuse-tegra30.o
scripts/Makefile.build:302: recipe for target 'drivers/soc/fsl/qe/qe.o' failed
make[4]: *** [drivers/soc/fsl/qe/qe.o] Error 1

-----Original Message-----
From: Valentin Longchamp [mailto:valentin.longch...@keymile.com] 
Sent: Friday, February 17, 2017 6:30 PM
To: linuxppc-dev@lists.ozlabs.org; Qiang Zhao <qiang.z...@nxp.com>
Cc: o...@buserror.net; Valentin Longchamp <valentin.longch...@keymile.com>
Subject: [PATCH 2/3] soc/fsl/qe: only apply QE_General4 workaround on affected 
SoCs

The QE_General4 workaround is only valid for the MPC832x and MPC836x SoCs. The 
other SoCs that embed a QUICC engine are not affected by this hardware bug and 
thus can use the computed divisors (this was successfully tested on the T1040).

Similalry to what was done in commit 8ce795cb0c6b ("i2c: mpc: assign the 
correct prescaler from SVR") in order to avoid changes in the device tree nodes 
of the QE (with maybe a variant of the compatible property), the PVR reg is 
read out to find out if the workaround must be applied or not.

Signed-off-by: Valentin Longchamp <valentin.longch...@keymile.com>
---
 drivers/soc/fsl/qe/qe.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index 
03874df..b66157fc 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -202,6 +202,9 @@ unsigned int qe_get_brg_clk(void)  }  
EXPORT_SYMBOL(qe_get_brg_clk);
 
+#define PVR_VER_836x   0x8083
+#define PVR_VER_832x   0x8084
+
 /* Program the BRG to the given sampling rate and multiplier
  *
  * @brg: the BRG, QE_BRG1 - QE_BRG16
@@ -228,8 +231,9 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, 
unsigned int multiplier)
        /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
           that the BRG divisor must be even if you're not using divide-by-16
           mode. */
-       if (!div16 && (divisor & 1) && (divisor > 3))
-               divisor++;
+       if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
+               if (!div16 && (divisor & 1) && (divisor > 3))
+                       divisor++;
 
        tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
                QE_BRGC_ENABLE | div16;
--
1.8.3.1

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