This patch series update ppc64 to use a 68 bit virtual address. The goal here is to help us increase the effective address range to 512TB. I still haven't comeup with a mechanism to enable application to selectively use address about the 64TB (the current limit). The last patch in this series is just to check whether the 68 bit va limit is working as expected.
On p4 and p5 which can do only 65 bit va, we do use mmu feature to fixup the max va bits. We do that by limiting the max context on these platforms. The context bits for these platforms get reduced from 19 bits to 16 bits with these patches. W.r.t limitting max effective address for application, we have discussion happening on lkml w.r.t different approaches that can be used. Once we reach concensus on that, the same approach can be used on ppc64 too. https://lkml.kernel.org/r/20161227015413.187403-30-kirill.shute...@linux.intel.com TODO: * PR kvm need to be looked at to study the impact * Limit max address to 64TB by default and selectively enable range above. * Fixup context switch to copy only required slice array. Aneesh Kumar K.V (5): powerpc/mm/slice: Convert slice_mask high slice to a bitmap powerpc/mm/slice: Update the function prototype powerpc/mm/hash: Move kernel context to the starting of context range powerpc/mm/hash: Support 68 bit VA powerpc/mm/hash: Increase VA range to 256TB arch/powerpc/include/asm/book3s/64/hash-4k.h | 2 +- arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +- arch/powerpc/include/asm/book3s/64/mmu-hash.h | 162 +++++++++++++++----------- arch/powerpc/include/asm/mmu.h | 19 ++- arch/powerpc/include/asm/mmu_context.h | 2 - arch/powerpc/include/asm/page_64.h | 15 +-- arch/powerpc/include/asm/processor.h | 12 +- arch/powerpc/kvm/book3s_64_mmu_host.c | 2 +- arch/powerpc/mm/hash_utils_64.c | 5 - arch/powerpc/mm/mmu_context_book3s64.c | 87 +++++++++----- arch/powerpc/mm/slb_low.S | 71 +++++++---- arch/powerpc/mm/slice.c | 147 ++++++++++++++--------- 12 files changed, 318 insertions(+), 208 deletions(-) -- 2.7.4
