Those come from
XSL_databook_09_June_2014.pdf
The registers in this doc listed at 0x400-600 are offset by 0x400, so 0x568 = 0x168.
John Walthour
Development Engineer
IBM Corporation | Systems & Technology Group
Phone: (512) 973-1095 | T/L: 363-1095
Email: jwalth...@us.ibm.com
return 0
Development Engineer
IBM Corporation | Systems & Technology Group
Phone: (512) 973-1095 | T/L: 363-1095
Email: jwalth...@us.ibm.com
return 0
----- Original message -----
From: Frederic Barrat <fbar...@linux.vnet.ibm.com>
Sent by: "Linuxppc-dev" <linuxppc-dev-bounces+jwalthour=us.ibm....@lists.ozlabs.org>
To: Ian Munsie <imun...@au1.ibm.com>, Michael Ellerman <m...@ellerman.id.au>, mikey <mi...@neuling.org>, linuxppc-dev@lists.ozlabs.org, Frederic Barrat <frederic.bar...@fr.ibm.com>, Huy Nguyen <h...@mellanox.com>
Cc:
Subject: Re: [PATCH] cxl: Abstract the differences between the PSL and XSL
Date: Fri, May 27, 2016 7:49 AM
Hi Ian,
It looks good, just one question:
> +/* XSL registers (Mellanox CX4) */
> +static const cxl_p1_reg_t CXL_XSL_Timebase = {0x0100};
> +static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
> +static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};
> +static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};
Out of curiosity, in which document did you get those offsets from? I
remember there used to be some confusion about it. All I could find was
the internal offsets the firmware remaps those to (in xsl databook).
Feel free to grab the "From:", since the patch has evolved since I
worked on it. I don't care.
Fred
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