Grant Likely wrote: > On 9/14/07, Matt Sealey <[EMAIL PROTECTED]> wrote: >> sparse, irq_of_find_and_map isn't much help). Maybe I am just not >> looking in the right place but not being an MPC52xx PIC Expert I >> wouldn't even know where to start... > > The l2 irq numbers map directly to the interrupt numbers listed in the > 5200b user guide. For example, on p7-11, the masks are listed for > main interrupts 0 through 16. and on p7-17,18, the peripherial > interrupts are listed as numbered from 0 to 23 (but notice that it > does *not* line up with bit positions).
Wow I even had to search.. it's on p7-13 here.. Right but it does start from a certain bit and progress linearly across the rest of the register. However, what is interrupt 0 and what is interrupt 16? Do you start from the left or the right (i.e. Motorola big endian or Rest Of World big endian)?? > However, it is interesting to note that other than in the register > definitions, I don't think there is anywhere in the 5200b user manual > that simple lists the interrupt numbers for each interrupt type. I think the interesting note is that picking out "what does IRQ 4 in the main interrupt group handle" or picking out a device and saying "this is IRQ 10" is still, even with your explanation, a matter of luck and handedness. Personally I would count from the right (Motorola bit 31) and work my way from LSB to MSB, but Motorola likes it's backwards representation and so do some other people. So, does bit 31 equal interrupt 0 or interrupt 16? :) Then there are the status encoded registers, which report which IRQ is firing. They are just values. But which value corresponds to which interrupt (left or right reading) here or do they even have completely different ones? -- Matt Sealey <[EMAIL PROTECTED]> Genesi, Manager, Developer Relations _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
