Linas Vepstas wrote: > On Mon, Jul 30, 2007 at 01:17:40PM -0700, Dave Jiang wrote: >> Arnd Bergmann wrote: >>> The best solution may be to look at how it's structured at the >>> register level. If the PCI EDAC registers are implemented separately >>> from the regular PCI registers, a device tree entry would be appropriate. >>> If not, your idea of registering a platform_device from fsl_add_bridge >>> is probably more sensible. >>> >> We can probably do either. From looking at the 8560 and 8548 manuals, the PCI >> error registers are 0xe00 offset of the start of PCI registers. For example, >> the PCI registers would start at 0x8000 offset. And the PCI error registers >> would be at 0xe00 offset from there and would be the very last block of >> registers. > > Anywhere I can easily get an overview of these "PCI error registers"?
http://www.freescale.com/files/32bit/doc/ref_manual/MPC8548ERM.pdf?fsrch=1 Page 966. Section 16.3.1.4. Is this what you mean? _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
