rx_lanes and tx_lanes sysfs entries show the number of lanes in use by a
device.
USB 3.2 adds support for Dual-lane (symmetrical), using 2 rx lanes and
2 tx lanes for normal non Inter-Chip SSIC devices.
USB 3.1 and older are all single lane.

SSIC devices can have up to 4 lanes per direction in use,
with different number of rx and tx lanes.

Signed-off-by: Mathias Nyman <[email protected]>
---
 Documentation/ABI/testing/sysfs-bus-usb | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/ABI/testing/sysfs-bus-usb 
b/Documentation/ABI/testing/sysfs-bus-usb
index c702c78..c6e9b30 100644
--- a/Documentation/ABI/testing/sysfs-bus-usb
+++ b/Documentation/ABI/testing/sysfs-bus-usb
@@ -236,3 +236,21 @@ Description:
                Supported values are 0 - 15.
                More information on how besl values map to microseconds can be 
found in
                USB 2.0 ECN Errata for Link Power Management, section 4.10)
+
+What:          /sys/bus/usb/devices/.../rx_lanes
+Date:          March 2018
+Contact:       Mathias Nyman <[email protected]>
+Description:
+               Number of rx lanes the device is using.
+               USB 3.2 adds Dual-lane support, 2 rx and 2 tx lanes over Type-C.
+               Inter-Chip SSIC devices support asymmetric lanes up to 4 lanes 
per
+               direction. Devices before USB 3.2 are single lane (rx_lanes = 1)
+
+What:          /sys/bus/usb/devices/.../tx_lanes
+Date:          March 2018
+Contact:       Mathias Nyman <[email protected]>
+Description:
+               Number of tx lanes the device is using.
+               USB 3.2 adds Dual-lane support, 2 rx and 2 tx -lanes over 
Type-C.
+               Inter-Chip SSIC devices support asymmetric lanes up to 4 lanes 
per
+               direction. Devices before USB 3.2 are single lane (tx_lanes = 1)
-- 
2.7.4

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