On Wed, Feb 28, 2024 at 05:01:21PM -0800, Atish Patra wrote:
> The virtual counter value is updated during pmu_ctr_read. There is no need
> to update it in reset case. Otherwise, it will be counted twice which is
> incorrect.
>
> Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling")
> Reviewed-by: Anup Patel <a...@brainfault.org>
> Signed-off-by: Atish Patra <ati...@rivosinc.com>
> ---
> arch/riscv/kvm/vcpu_pmu.c | 8 ++------
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
> index 86391a5061dd..b1574c043f77 100644
> --- a/arch/riscv/kvm/vcpu_pmu.c
> +++ b/arch/riscv/kvm/vcpu_pmu.c
> @@ -397,7 +397,6 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,
> unsigned long ctr_base,
> {
> struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
> int i, pmc_index, sbiret = 0;
> - u64 enabled, running;
> struct kvm_pmc *pmc;
> int fevent_code;
>
> @@ -432,12 +431,9 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu,
> unsigned long ctr_base,
> sbiret = SBI_ERR_ALREADY_STOPPED;
> }
>
> - if (flags & SBI_PMU_STOP_FLAG_RESET) {
> - /* Relase the counter if this is a reset
> request */
> - pmc->counter_val +=
> perf_event_read_value(pmc->perf_event,
> -
> &enabled, &running);
> + if (flags & SBI_PMU_STOP_FLAG_RESET)
> + /* Release the counter if this is a reset
> request */
> kvm_pmu_release_perf_event(pmc);
> - }
> } else {
> sbiret = SBI_ERR_INVALID_PARAM;
> }
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
