On Fri, Oct 16, 2015 at 05:18:30PM +0200, Peter Zijlstra wrote:
> Hi,
>
> IIRC Paul relies on schedule() implying a full memory barrier with
> strong transitivity for RCU.
>
> If not, ignore this email.
Not so sure about schedule(), but definitely need strong transitivity
for the rcu_node structure's ->lock field. And the atomic operations
on the rcu_dyntick structure's fields when entering or leaving the
idle loop.
With schedule, the thread later reports the quiescent state, which
involves acquiring the rcu_node structure's ->lock field. So I -think-
that the locks in the scheduler can be weakly transitive.
> If so, however, I suspect AARGH64 is borken and would need (just like
> PPC):
>
> #define smp_mb__before_spinlock() smp_mb()
>
> The problem is that schedule() (when a NO-OP) does:
>
> smp_mb__before_spinlock();
> LOCK rq->lock
>
> clear_bit()
>
> UNLOCK rq->lock
>
> And nothing there implies a full barrier on AARGH64, since
> smp_mb__before_spinlock() defaults to WMB, LOCK is an "ldaxr" or
> load-acquire, UNLOCK is "stlrh" or store-release and clear_bit() isn't
> anything.
>
> Pretty much every other arch has LOCK implying a full barrier, either
> because its strongly ordered or because it needs one for the ACQUIRE
> semantics.
Well, arm64 might well need smp_mb__after_unlock_lock() to be non-empty.
But I thought that it used a dmb in the spinlock code somewhere or
another...
Thanx, Paul
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