On 10/2/15, Peter Bergner <berg...@vnet.ibm.com> wrote: > On Fri, 2015-10-02 at 22:03 +0300, Denis Kirjanov wrote: >> arch/powerpc/kernel/swsusp_asm64.S: Assembler messages: >>> arch/powerpc/kernel/swsusp_asm64.S:188: Error: missing operand >>> scripts/Makefile.build:294: recipe for target >>> 'arch/powerpc/kernel/swsusp_asm64.o' failed >>> make[1]: *** [arch/powerpc/kernel/swsusp_asm64.o] Error 1 >>> Makefile:941: recipe for target 'arch/powerpc/kernel' failed >>> make: *** [arch/powerpc/kernel] Error 2 > [snip] >>> I don't know enough ppc assembly to properly fix this but I can test. >> >> Could you please test the patch attached? > [snip] >> -0: tlbie r4; \ >> +0: tlbie r4, 0; \ > > This isn't correct. With POWER7 and later (which this compile > is, since it's on LE), the tlbie instruction takes two register > operands: > > tlbie RB, RS > > The tlbie instruction on pre POWER7 cpus had one required register > operand (RB) and an optional second L operand, where if you omitted > it, it was the same as using "0": > > tlbie RB, L > > This is a POWER7 and later build, so your change which adds the "0" > above is really adding r0 for RS. The new tlbie instruction doesn't > treat r0 specially, so you'll be using whatever random bits which > happen to be in r0 which I don't think that is what you want.
Ok, than we can just zero out r5 for example and use it in tlbie as RS, right? > > > Peter > > > >
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index dd0fc18..cb0f627 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -443,9 +443,10 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945) #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) #define tlbia \ li r4,1024; \ + li r5,0; \ mtctr r4; \ lis r4,KERNELBASE@h; \ -0: tlbie r4; \ +0: tlbie r4, r5; \ addi r4,r4,0x1000; \ bdnz 0b #endif
