On Wed, Jun 17, 2015 at 09:47:08AM +0200, Paolo Bonzini wrote:
> On 17/06/2015 02:36, Andy Lutomirski wrote:
> > __pvclock_read_cycles had an unnecessary barrier. Get rid of that
> > barrier and clean up the code by just using rdtsc_ordered().
> >
> > Cc: Paolo Bonzini <pbonz...@redhat.com>
> > Cc: Radim Krcmar <rkrc...@redhat.com>
> > Cc: Marcelo Tosatti <mtosa...@redhat.com>
> > Cc: k...@vger.kernel.org
> > Signed-off-by: Andy Lutomirski <l...@kernel.org>
> > ---
> >
> > I'm hoping to get an ack for this to go in through -tip. (Arguably
> > I'm the maintainer of this code given how it's used, but I should
> > still ask for an ack.)
> >
> > arch/x86/include/asm/pvclock.h | 21 ++++++++++++---------
> > 1 file changed, 12 insertions(+), 9 deletions(-)
>
> Can you send a URL to the rest of the series? I've never even seen v1
> or v2 so I have no idea of what this is about.
>
> > diff --git a/arch/x86/include/asm/pvclock.h b/arch/x86/include/asm/pvclock.h
> > index 6084bce345fc..cf2329ca4812 100644
> > --- a/arch/x86/include/asm/pvclock.h
> > +++ b/arch/x86/include/asm/pvclock.h
> > @@ -62,7 +62,18 @@ static inline u64 pvclock_scale_delta(u64 delta, u32
> > mul_frac, int shift)
> > static __always_inline
> > u64 pvclock_get_nsec_offset(const struct pvclock_vcpu_time_info *src)
> > {
> > - u64 delta = rdtsc() - src->tsc_timestamp;
> > + /*
> > + * Note: emulated platforms which do not advertise SSE2 support
> > + * break rdtsc_ordered, resulting in kvmclock not using the
> > + * necessary RDTSC barriers. Without barriers, it is possible
> > + * that RDTSC instruction is executed before prior loads,
> > + * resulting in violation of monotonicity.
> > + *
> > + * On an SMP guest without SSE2, it's unclear how anything is
> > + * supposed to work correctly, though -- memory fences
> > + * (e.g. smp_mb) are important for more than just timing.
> > + */
>
> On an SMP guest without SSE2, memory fences are obtained with e.g. "lock
> addb $0, (%esp)".
Yeah, I killed that comment when applying.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
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