On Mon, Jun 15, 2015 at 2:42 PM, H. Peter Anvin <h...@zytor.com> wrote: > On 06/15/2015 02:30 PM, Linus Torvalds wrote: >> >> On Jun 12, 2015 2:09 PM, "Andy Lutomirski" <l...@amacapital.net >> <mailto:l...@amacapital.net>> wrote: >>> >>> Caveat emptor: it also disables SMP. >> >> OK, I don't think it's interesting in that form. >> >> For small cpu counts, I guess we could have per-cpu syscall entry points >> (unless the syscall entry msr is shared across hyperthreading? Some >> msr's are per thread, others per core, AFAIK), and it could actually >> work that way. >> >> But I'm not sure the three cycles is worth the worry and the complexity. >> > > We discussed the per-cpu syscall entry point, and the issue at hand is > that it is very hard to do that without with fairly high probability > touch another cache line and quite possibly another page (and hence a > TLB entry.)
I think this isn't actually true. If we were going to do a per-cpu syscall entry point, then we might as well duplicate all of the entry code per cpu instead of just a short trampoline. That would avoid extra TLB misses and (L1) cache misses, I think. I still think this is far too complicated for three cycles. I was hoping for more. --Andy -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
