On Wed, May 13, 2015 at 07:16:34AM +0000, Lior Amsalem wrote: > > From: Andrew Lunn [mailto:and...@lunn.ch] > > Sent: Tuesday, May 12, 2015 7:13 PM > > > > On Tue, May 12, 2015 at 05:37:43PM +0200, Maxime Ripard wrote: > > > From: Lior Amsalem <al...@marvell.com> > > > > > > The new XOR engine has a new compatible of its own, together with new > > > channel capabilities. > > > > > > Use that new compatible now that we have a driver that can handle it. > > > > > > Signed-off-by: Lior Amsalem <al...@marvell.com> > > > Reviewed-by: Ofer Heifetz <of...@marvell.com> > > > Reviewed-by: Nadav Haklai <nad...@marvell.com> > > > Tested-by: Nadav Haklai <nad...@marvell.com> > > > --- > > > arch/arm/boot/dts/armada-38x.dtsi | 20 ++++++-------------- > > > 1 file changed, 6 insertions(+), 14 deletions(-) > > > > > > diff --git a/arch/arm/boot/dts/armada-38x.dtsi > > > b/arch/arm/boot/dts/armada-38x.dtsi > > > index ed2dd8ba4080..6d07b7389415 100644 > > > --- a/arch/arm/boot/dts/armada-38x.dtsi > > > +++ b/arch/arm/boot/dts/armada-38x.dtsi > > > @@ -448,7 +448,7 @@ > > > }; > > > > > > xor@60800 { > > > - compatible = "marvell,orion-xor"; > > > + compatible = "marvell,a38x-xor"; > > > reg = <0x60800 0x100 > > > 0x60a00 0x100>; > > > clocks = <&gateclk 22>; > > > @@ -458,17 +458,13 @@ > > > interrupts = <GIC_SPI 22 > > IRQ_TYPE_LEVEL_HIGH>; > > > dmacap,memcpy; > > > dmacap,xor; > > > - }; > > > - xor01 { > > > - interrupts = <GIC_SPI 23 > > IRQ_TYPE_LEVEL_HIGH>; > > > - dmacap,memcpy; > > > - dmacap,xor; > > > - dmacap,memset; > > > + dmacap,pq; > > > + dmacap,interrupt; > > > > Does this mean the hardware only has one channel? > > And memset is no longer supported? > > > > The hardware has two channels per engine and two engines. > However, both on HW side (both channels are on the same "bus port") > and SW (the dma subsystem will assign one channel per CPU). > we found it's better (performance wise) to use only one channel on each engine > and let the framework assign one per CPU. > This way, descriptors chaining was better (cause of the depended descriptors > problem) and overall interrupt number reduced. > > Yes, since memset is a problematic one. It can only be done via registers > (and not on descriptors level) plus no one really needs it...
And memset support has been removed from dmaengine since 3.11, so it doesn't look like anyone really needs it :) We're talking about reintroducing it for some platforms that actually need it, but it wasn't really used on marvell anyway... Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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