On Thu, Apr 23, 2015 at 6:27 PM, Andy Lutomirski <l...@amacapital.net> wrote: > I'll go out on a limb and guess the present bit doesn't leak. If I > were implementing an x86 cpu, I wouldn't have a present bit at all in > the descriptor cache, since you aren't supposed to be able to load a > non-present descriptor in the first place.
There is definitely a present bit in cached descriptors. It is used to track whether NULL selector was loaded into this particular segment register. The bit is even visible in SMM save area. See table 10-1 in 24593_APM.pdf Naturally, CS can't be NULL, and up until today I thought SS also can't. But the bit is probably implemented for all eight cached descriptors. -- vda -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
