On Wed, Jan 28, 2015 at 09:31:49PM +0000, Timur Tabi wrote: > On Fri, Jul 4, 2014 at 2:28 AM, AKASHI Takahiro > <takahiro.aka...@linaro.org> wrote: > > +#define __ARM_NR_COMPAT_BASE 0x0f0000 > > +#define __ARM_NR_compat_cacheflush (__ARM_NR_COMPAT_BASE+2) > > +#define __ARM_NR_compat_set_tls (__ARM_NR_COMPAT_BASE+5) > > I know this patch is six months old, but I was wondering if anyone > knows of any plans to make these syscalls available to 64-bit apps? > We have a 32-bit app that uses __ARM_NR_compat_cacheflush, and we'd > like to port that app to 64-bit. I'm just not sure how to start doing > that, since there don't appear to be any 64-bit ARM-specific syscalls.
You can issue cache maintenance instructions directly from EL0 in AArch64. Take a look at DC CVAU, DC CVAC, DC CIVAC, IC IVAU and DC ZVA. As for the TLS register, that's also writable from EL0 but I wouldn't recommend messing with it outside of libc. Will -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
