Add compatible strings for the SOR IP blocks present on several Tegra
chips.  The primary objective here is to avoid checkpatch warnings,
per:

http://marc.info/?l=linux-tegra&m=142201349727836&w=2

Signed-off-by: Paul Walmsley <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: "Terje Bergström" <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Pawel Moll <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Ian Campbell <[email protected]>
Cc: Kumar Gala <[email protected]>
Cc: Stephen Warren <[email protected]>
Cc: Alexandre Courbot <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
 .../bindings/gpu/nvidia,tegra20-host1x.txt         |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt 
b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index 4c32ef0b7db8..0e828c00e7e4 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -198,6 +198,7 @@ of the following host1x client modules:
 
   Required properties:
   - compatible: "nvidia,tegra124-sor"
+    "nvidia,tegra132-sor" (not yet matched in the driver)
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
   - clocks: Must contain an entry for each entry in clock-names.
@@ -223,6 +224,7 @@ of the following host1x client modules:
 
 - dpaux: DisplayPort AUX interface
   - compatible: "nvidia,tegra124-dpaux"
+    "nvidia,tegra132-dpaux" (not yet matched in the driver)
   - reg: Physical base address and length of the controller's registers.
   - interrupts: The interrupt outputs from the controller.
   - clocks: Must contain an entry for each entry in clock-names.


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