On Thu, Nov 13, 2014 at 5:29 AM, Arnd Bergmann <a...@arndb.de> wrote:
> On Tuesday 28 October 2014 08:36:54 suravee.suthikulpa...@amd.com wrote:
>> From: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
>>
>> Initial revision of device tree for AMD Seattle platform
>
> Sorry for not looking at this earlier in enough detail.
>
>> + dma0: dma@0500000 {
>> + compatible = "arm,pl330", "arm,primecell";
>> + reg = <0 0x0500000 0 0x1000>;
>> + interrupts =
>> + <0 368 4>,
>> + <0 369 4>,
>> + <0 370 4>,
>> + <0 371 4>,
>> + <0 372 4>,
>> + <0 373 4>,
>> + <0 374 4>,
>> + <0 375 4>;
>> + clocks = <&dmaclk_500mhz>;
>> + clock-names = "apb_pclk";
>> + #dma-cells = <1>;
>> + };
>
> Is this device cache-coherent?
>
> Does it support larger than 32-bit DMA addresses?
No.
>
>> + sata0: sata@00300000 {
>> + compatible = "snps,dwc-ahci";
This should have an AMD specific compatible string in addition in case
you have AMD specific configuration or bugs.
>> + reg = <0 0x300000 0 0x800>;
>> + interrupts = <0 355 4>;
>> + clocks = <&sataclk_333mhz>;
>> + clock-names = "apb_pclk";
This name is obviously wrong and copied from other (ARM Primecell)
bindings as this IP does not have an APB PCLK. You can drop the name
as it is optional.
>> + dma-coherent;
>> + };
>
> Same here: you list it as coherent, but not 64-bit DMA capable.
> Is that intentional?
AHCI controllers are probeable as to whether they support 64-bit DMA or not.
Rob
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