On Wed, Nov 5, 2014 at 6:58 PM, Yijing Wang <wangyij...@huawei.com> wrote:
>>> +{
>>> + return (irq_hw_number_t)msidesc->msi_attrib.entry_nr |
>>> + PCI_DEVID(pdev->bus->number, pdev->devfn) << 11 |
>>> + (pci_domain_nr(pdev->bus) & 0xFFFFFFFF) << 27;
>>
>> Where does this bit layout come from? Is this defined in the spec
>> somewhere? A reference would help.
>
> Currently, more and more Non-PCI device use MSI(or similar MSI mechanism),
> like DMAR fault irq
> and HPET FSB irq. And we have to add additional code to support the MSI
> capability.
> So I hope we can decouple MSI code and PCI code, then we can unify all MSI(or
> Message Based interrupt)
> in one framework.
Was that supposed to answer my question? If so, I didn't understand
how it explains where the bit layout came from.
Bjorn
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