On Tue, Oct 28, 2014 at 04:25:35PM +0000, Linus Torvalds wrote: > On Tue, Oct 28, 2014 at 9:07 AM, Will Deacon <[email protected]> wrote: > > I was certainly seeing this issue trigger regularly when running firefox, > > but I'll need to dig and find out the differences in range size. > > I'm wondering whether that was perhaps because of the mix-up with > initialization of the range. Afaik, that would always break your > min/max thing for the first batch (and since the batches are fairly > large, "first" may be "only") > > But hey. it's possible that firefox does some big mappings but only > populates the beginning. Most architectures don't tend to have > excessive glass jaws in this area: invalidating things page-by-page is > invariably so slow that at some point you just go "just do the whole > range". > > > Since we have hardware broadcasting of TLB invalidations on ARM, it is > > in our interest to keep the number of outstanding operations as small as > > possible, particularly on large systems where we don't get the targetted > > shootdown with a single message that you can perform using IPIs (i.e. > > you can only broadcast to all or no CPUs, and that happens for each pte). > > Do you seriously *have* to broadcast for each pte? > > Because that is quite frankly moronic. We batch things up in software > for a real good reason: doing things one entry at a time just cannot > ever scale. At some point (and that point is usually not even very far > away), it's much better to do a single invalidate over a range. The > cost of having to refill the TLB's is *much* smaller than the cost of > doing tons of cross-CPU invalidates.
I don't think that's necessarily true, at least not on the systems I'm familiar with. A table walk can be comparatively expensive, particularly when virtualisation is involved and the depth of the host and guest page tables starts to grow -- we're talking >20 memory accesses per walk. By contrast, the TLB invalidation messages are asynchronous and carried on the interconnect (a DSB instruction is used to synchronise the updates). > That's true even for the cases where we track the CPU's involved in > that mapping, and only invalidate a small subset. With a "all CPU's > broadcast", the cross-over point must be even smaller. Doing thousands > of CPU broadcasts is just crazy, even if they are hw-accelerated. > > Can't you just do a full invalidate and a SW IPI for larger ranges? We already do that, but it's mainly there to catch *really* large ranges (like the negative ones...), which can trigger the soft lockup detector. The cases we've seen for this so far have been bugs (e.g. this thread and also a related issue where we try to flush the whole of vmalloc space). > And as mentioned, true sparse mappings are actually fairly rare, so > making extra effort (and data structures) to have individual ranges > sounds crazy. Sure, I'll try and get some data on this. I'd like to resolve the THP case, at least, which means keeping track of calls to __tlb_remove_pmd_tlb_entry. > Is this some hw-enforced thing? You really can't turn off the > cross-cpu-for-each-pte braindamage? We could use IPIs if we wanted to and issue local TLB invalidations on the targetted cores, but I'd be surprised if this showed an improvement on ARM-based systems. Will -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
