On 09/16/2014 09:01 AM, Peter Zijlstra wrote:
> On Tue, Sep 16, 2014 at 02:03:00AM -0500, Chuck Ebbert wrote:
>> Hmm, looking closer at the diagram, each ring has its own memory controller, 
>> so
>> it really is NUMA if you break the interconnect between that caches.
> 
> How does it do that? Does it split the DIMM slots in two as well, with
> half for the one node and the other half for the other? Or will both
> 'nodes' share the same local memory?

I the diagrams in here are accurate in describing the rings:

http://www.enterprisetech.com/2014/09/08/intel-ups-performance-ante-haswell-xeon-chips/

The "nodes" each get their own memory controller and exclusive set of DIMMs.
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