On 27/08/14 23:33, Mukesh Rathor wrote: > This patch addresses three things for a pvh secondary vcpu:
I don't understand why you have separated this into two patches. Please fold into one. > Please note: We create a new glue assembly entry point because the > secondary vcpus come up on kernel page tables that have pte.NX > bits set. While on Intel these are ignored if EFER.NX is not set, on > AMD a RSVD bit fault is generated. Please try and unify the early CPU init code for boot and secondary CPUs. Native manages to do this (secondary_startup_64 is called for boot and secondary CPUs). > + /* Gather features to see if NX implemented. (no EFER.NX on intel) */ EFER.NXE does exist on Intel. David -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
