On Thu, 28 Aug 2014 15:18:26 +0100 David Vrabel <david.vra...@citrix.com> wrote:
> On 27/08/14 23:33, Mukesh Rathor wrote: > > This patch addresses three things for a pvh boot vcpu: > > > > - NX bug on intel: It was recenlty discovered that NX is not being > > honored in PVH on intel since EFER.NX is not being set. The > > pte.NX bits are ignored if EFER.NX is not set on intel. > > I am unconvinced by this explanation. The Intel SDM clearly states > that the XD bit in the page table entries is reserved if EFER.NXE is > clear, and thus using a entry with XD set and EFER.NXE clear should > generate a page fault (same as AMD). > > You either need to find out why Intel really worked (perhaps Xen is > setting EFER.NXE on Intel?) or you need to included an errata (or > similar) reference. Nop, verified that again. The vcpu is coming up on efer 0x501, ie, LME/LMA/SCE (older xen prior to SCE removal change). The pte entry for rsp is: 800000003e32b063 that has NX set. No exception is generated upon push rbp instruction (like on amd). Could be that Intel docs are incomplete on vmx, I didn't hear back from them on the last one I had found. Anyways, we are not addressing an intel errata here, but fixing our issue of setting the EFER.NX bit. -Mukesh -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
