On Fri, 22 Aug 2014 06:41:40 +0200 Borislav Petkov <b...@alien8.de> wrote:
> On Thu, Aug 21, 2014 at 07:46:56PM -0700, Mukesh Rathor wrote: > > Intel doesn't have EFER.NX bit. > > Of course it does. > Right, it does. Some code/comment is misleading... Anyways, reading intel SDMs, if I understand the convoluted text correctly, EFER.NX is not required to be set for l1.nx to be set, thus allowing for page level protection. Where as on AMD, EFER.NX must be set for l1.nx to be used. So, in the end, this patch would apply to both amd/intel.... I'll reword and submit. Thanks, Mukesh -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
