Russell King wrote:
>I, therefore, strongly suggest that you arrange to do
the same - iow,
>deassert RTS when your buffer is approaching approx.
2/3 full rather
>than absolutely full.
Well, I don't think this gonna work because my rx fifo
is only 8 bytes
length and 8250's one is 16 bytes length. This means
that if I
deassert RTS when my fifo is 5 bytes full, I can
potentially receive 8
bytes and thus get an overrun...
But why should I "degrade" my UART because some 8250
devices have
poor hardware implementation. Maybe we should limit
their tx fifo to
one byte when rts/cts flow control is enabled...
thanks
Francis
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