On Wed, May 28, 2014 at 07:05:51PM +0200, Stephane Eranian wrote: > On Wed, May 28, 2014 at 6:51 PM, Andi Kleen <[email protected]> wrote: > >> The only part I don't quite follow here is this: > >> if (__test_and_set_bit(bit, (unsigned long > >> *)&status)) > >> continue; > >> > >> Which seems to indicate the code is making sure each counter is > >> processed only once. But it can only be processed once, if you have > >> only one record. And if you have multiple, you want to be able to > >> handle the same counter multiple times, at least once perf PEBS > >> record. So I am a bit confused about this test. > > > > Each PEBS record is only for a single counter overflow. So it > > always should only be a single perf event. > > > So, you're telling me this is a sanity check. That p->status can > only have one bit set. Somehow that's not how I recall it working. > > The point is that a single PEBS record is enough for multiple > events when the overflows occur simultaneously because they > all get the same machine state which is correct. A single entry > also saves space in the buffer.
Confusion reigns.. now if only someone would write all this down in a coherent manner and give it an official Intel stamp of approval ;-)
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