On Mon, Mar 03, 2014 at 07:41:17PM +0100, Peter Zijlstra wrote: > On Mon, Mar 03, 2014 at 01:07:00PM -0500, Joe Mario wrote: > > If you only sample on the HITMs then you don't get the store misses. > > That means you'll not be able to detect who is simultaneously tugging > > on the same cache lines. That gives up much of the value of "perf > > c2c". > > As long as you know which lines are hurting bringing in (loads) you can > often figure out who is doing the stores on them.
If you are familar with the code I guess. One scenario that would be difficult for is shared memory (ie databases) as it may not be obvious who is writing to a cacheline. > > > As we developed this, we ended up settling on Ivy Bridge to get the > > behavior we wanted. > > Wouldn't SNB also work? We started with SNB, but because latency info was not working (due to a GO bug) and some other event quirks, we found ourselves migrating to a more stable IVB platform instead. Now that we stablized our test case and tool, SNB may work. We just haven't tried in along time. Cheers, Don -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
