On Wed, Oct 02, 2013 at 11:11:06AM -0500, suravee.suthikulpa...@amd.com wrote: > From: Jacob Shin <jacob.w.s...@gmail.com> > > Implement hardware breakpoint address mask for AMD Family 16h and > above processors. CPUID feature bit indicates hardware support for > DRn_ADDR_MASK MSRs. These masks further qualify DRn/DR7 hardware > breakpoint addresses to allow matching of larger addresses ranges. > > Valuable advice and pseudo code from Oleg Nesterov <o...@redhat.com> > > Signed-off-by: Jacob Shin <jacob.w.s...@gmail.com> > Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com> > --- > arch/x86/include/asm/cpufeature.h | 2 ++ > arch/x86/include/asm/debugreg.h | 5 ++++ > arch/x86/include/asm/hw_breakpoint.h | 1 + > arch/x86/include/uapi/asm/msr-index.h | 4 +++ > arch/x86/kernel/cpu/amd.c | 19 ++++++++++++++ > arch/x86/kernel/hw_breakpoint.c | 47 > ++++++++++++++--------------------- > 6 files changed, 49 insertions(+), 29 deletions(-) > > diff --git a/arch/x86/include/asm/cpufeature.h > b/arch/x86/include/asm/cpufeature.h > index d3f5c63..26609bb 100644 > --- a/arch/x86/include/asm/cpufeature.h > +++ b/arch/x86/include/asm/cpufeature.h > @@ -170,6 +170,7 @@ > #define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ > #define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter > extensions */ > #define X86_FEATURE_PERFCTR_NB (6*32+24) /* NB performance counter > extensions */ > +#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
Does this feature only work on data breakpoint or is instruction breakpoint address range supported as well? -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
