On 07/18/2013 11:21 PM, Zubair Lutfullah wrote:
> From: "Patil, Rachna" <rac...@ti.com>
> 
> ADC is ideally expected to work at a frequency of 3MHz.
> The present code had a check, which returned error if the frequency
> went below the threshold  value. But since AM335x supports various
> working frequencies, this check is not required.
> Now the code just uses the internal ADC clock divider to set the ADC
> frequency w.r.t the sys clock.
A I read this comment, this is a fairly stand alone patch and everything
else in the series will work whether or not it is there?

If so, should not really be part of this series and I'm certainly
going to leave taking it up to the mfd maintainer.
> 
> Signed-off-by: Patil, Rachna <rac...@ti.com>
> Signed-off-by: Zubair Lutfullah <zubair.lutful...@gmail.com>
> ---
>  drivers/mfd/ti_am335x_tscadc.c       |    6 +-----
>  include/linux/mfd/ti_am335x_tscadc.h |    1 -
>  2 files changed, 1 insertion(+), 6 deletions(-)
> 
> diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c
> index 9f5c326..b8d7dfb 100644
> --- a/drivers/mfd/ti_am335x_tscadc.c
> +++ b/drivers/mfd/ti_am335x_tscadc.c
> @@ -197,11 +197,7 @@ static   int ti_tscadc_probe(struct platform_device 
> *pdev)
>       clock_rate = clk_get_rate(clk);
>       clk_put(clk);
>       clk_value = clock_rate / ADC_CLK;
> -     if (clk_value < MAX_CLK_DIV) {
> -             dev_err(&pdev->dev, "clock input less than min clock 
> requirement\n");
> -             err = -EINVAL;
> -             goto err_disable_clk;
> -     }
> +
>       /* TSCADC_CLKDIV needs to be configured to the value minus 1 */
>       clk_value = clk_value - 1;
>       tscadc_writel(tscadc, REG_CLKDIV, clk_value);
> diff --git a/include/linux/mfd/ti_am335x_tscadc.h 
> b/include/linux/mfd/ti_am335x_tscadc.h
> index 3058aef..136463b 100644
> --- a/include/linux/mfd/ti_am335x_tscadc.h
> +++ b/include/linux/mfd/ti_am335x_tscadc.h
> @@ -127,7 +127,6 @@
>  #define SEQ_STATUS BIT(5)
>  
>  #define ADC_CLK                      3000000
> -#define      MAX_CLK_DIV             7
>  #define TOTAL_STEPS          16
>  #define TOTAL_CHANNELS               8
>  #define FIFO1_THRESHOLD              19
> 
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