On 06/18/2013 08:59 AM, Borislav Petkov wrote:
> On Tue, Jun 18, 2013 at 10:07:30AM -0400, Dave Jones wrote:
>> My intent here was to ignore cases where the reserved bits haven't
>> been set. I occasionally see DR6: 00000000fffe0ff0 for eg.
>
> That's bit 16 which, according to the docs is read-as-1:
>
> "All remaining bits in the DR6 register are reserved. Reserved bits
> 31:16 and 11:4 must all be set to 1, while reserved bit 12 must be
> cleared to 0. In 64-bit mode, the upper 32 bits of DR6 are reserved and
> must be written with zeros. Writing a 1 to any of the upper 32 bits
> results in a general-protection exception, #GP(0)."
>
> This above if from AMD APM and Intel's SDM has a graphic showing the
> exact same thing:
>
> [31:16] = set to 1; [12] = 0b, [11:4] = 1b
>
> So if you see bit 16 cleared, then some BIOS or even hardware is doing
> funky things. I wouldn't wonder at all if BIOS dudes used reserved bits
> in registers as scratch space.
>
>> But maybe you're right, and that is a clue and is worth printing ? I
>> can't personally recall ever diagnosing a bug using those register
>> dumps in the last 15 years.
>
> Right, I don't know whether it would always help but if you have an
> oops and see, say bit 0 in DR6 set, i.e. a debug exception was caused
> by address breakpoint condition in DR0, then that could be useful info,
> methinks.
>
There is serious confusion with regards to DR6 about the bits which are
*fixed* (forced to 1) and the ones which are *reserved* (should always
have a fixed value.)
There are some bits in DR6 which are used by hardware probes.
-hpa
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