On Tue, Apr 23, 2013 at 09:34:23AM -0500, Jacob Shin wrote: > On Tue, Apr 23, 2013 at 10:54:37AM +0100, Will Deacon wrote: > > Hi Jacob, > > > > On Tue, Apr 23, 2013 at 08:57:02AM +0100, Jacob Shin wrote: > > > Some architectures (for us, AMD Family 16h) allow for "don't care" bit > > > mask to further qualify a hardware breakpoint address, in order to > > > trap on range of addresses. Update perf uapi to add bp_addr_mask field. > > > > arm and arm64 have a similar feature to this, whereby we currently have to > > translate the bp_len field into a mask, which is all the hardware > > understands. Unlike what you describe, our mask indicates the bytes we *are* > > interested in, but I think we could make use of the same functionality that > > you're introducing here. > > > > There are some funky restrictions on the alignment of the base address, but > > we can detect those and tell userspace where to go if it tries any funny > > stuff. > > > > Can you see a problem if I simply invert the mask? > > Hi, > > That's great! No, I don't see a problem at all. > > I guess now it can be debated if the mask coming in from userland should > be include or exclude mask. But I think exclude makes syntax easier: > > To count writes to [0x1000 ~ 0x1010) > > Include mask (my current patchset): ^^^^^^^ Exclude (I mean ..) > > perf stat -e mem:0x1000/0xf:w a.out > > Exclude mask: ^^^^^^^ Include > > perf stat -e mem:0x1000/0xfff0:w a.out > > Thanks!
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