On 03/27/2013 11:48 AM, Dan Williams wrote:
On Tue, Mar 26, 2013 at 3:43 PM, Dave Jiang <dave.ji...@intel.com> wrote:
The PQ Val ops work on the newer hardware so we should actually provide support
for it and remove the disabling bits.
Signed-off-by: Dave Jiang <dave.ji...@intel.com>
---
drivers/dma/Kconfig | 2 -
drivers/dma/ioat/dma.h | 1
drivers/dma/ioat/dma_v3.c | 134 ++++++++++++++++++++++++++++++++++++++----
drivers/dma/ioat/registers.h | 2 +
4 files changed, 125 insertions(+), 14 deletions(-)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 80b6997..dec088d 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -63,8 +63,6 @@ config INTEL_IOATDMA
depends on PCI && X86
select DMA_ENGINE
select DCA
- select ASYNC_TX_DISABLE_PQ_VAL_DMA
- select ASYNC_TX_DISABLE_XOR_VAL_DMA
help
Enable support for the Intel(R) I/OAT DMA engine present
in recent Intel Xeon chipsets.
[..]
@@ -1469,15 +1581,13 @@ int ioat3_dma_probe(struct ioatdma_device *device, int
dca)
device->cleanup_fn = ioat3_cleanup_event;
device->timer_fn = ioat3_timer_event;
- #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
- dma_cap_clear(DMA_PQ_VAL, dma->cap_mask);
- dma->device_prep_dma_pq_val = NULL;
- #endif
+ if (is_xeon_cb32(pdev)) {
+ dma_cap_clear(DMA_XOR_VAL, dma->cap_mask);
+ dma->device_prep_dma_xor_val = NULL;
- #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
- dma_cap_clear(DMA_XOR_VAL, dma->cap_mask);
- dma->device_prep_dma_xor_val = NULL;
- #endif
+ dma_cap_clear(DMA_PQ_VAL, dma->cap_mask);
+ dma->device_prep_dma_pq_val = NULL;
+ }
Note that this effectively disables raid offload for is_xeon_cb32()
platforms since DMA_ASYNC_TX will not be set.
We are ok with that until a workaround can be figured out.
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