On 3/14/2013 4:07 PM, Philip Avinash wrote: > da850 platforms require TBCLK synchronization in CFG_CHIP1 register for > TBCLK enable in EHRPWM modules. Enabling of TBCLK is done only if EHRPWM > DT node status is set to "okay" DT blob. > Also adds macro definitions for DA8XX_EHRPWM_TBCLKSYNC and > DA8XX_CFGCHIP1_REG.
So there is actually a TBCLK in DA850 - it's just not modeled as a clock similar to the way it is done on AM335x? If yes, then instead of adding a dummy clock node and doing the TBCLK enable as part of init, why not model TBCLK in clock tree even on DA850? Thanks, Sekhar -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
