From: ShuoX Liu <shuox....@intel.com>
These three chip are based on Atom and have different model id.
So add such three id for perf HW event support.
Signed-off-by: ShuoX Liu <shuox....@intel.com>
---
arch/x86/kernel/cpu/perf_event_intel.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c
b/arch/x86/kernel/cpu/perf_event_intel.c
index 93b9e11..c788e5f 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2019,6 +2019,9 @@ __init int intel_pmu_init(void)
break;
case 28: /* Atom */
+ case 38: /* Lincroft */
+ case 39: /* Penwell */
+ case 53: /* Cloverview */
case 54: /* Cedariew */
memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
--
1.7.1
--
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