The timers are common to both A9 cores, so let's set the clock
event struct's cpumask accordingly, to all possible CPUs.
Signed-off-by: Soren Brinkmann <soren.brinkm...@xilinx.com>
Reviewed-by: Josh Cartwright <josh.cartwri...@ni.com>
---
arch/arm/mach-zynq/timer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 7b2e047..f9fbc9c 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -267,6 +267,7 @@ static void __init zynq_ttc_setup_clockevent(struct
device_node *np,
ttcce->ce.set_mode = xttcps_set_mode;
ttcce->ce.rating = 200;
ttcce->ce.irq = irq;
+ ttcce->ce.cpumask = cpu_possible_mask;
__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPS_CNT_CNTRL_OFFSET);
__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
--
1.8.0.2
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