On 8/21/2012 5:05 PM, Arnd Bergmann wrote:
> It should be easy to tell from the object code whether this happened
> or not. If it did, then we can investigate why gcc did that, otherwise
> something else caused the strange byte swap.
>
> The safe way to define the readl() function in asm/io.h is to
> use an inline assembly that prevents the access from getting split,
> but avr32 just uses a pointer dereference here.
>
> I think I just found the answer elsewhere in
> arch/avr32/mach-at32ap/include/mach/io.h, which defines
>
> # define __mem_ioswabl(a, x) swahb32(x)
>
> and that apparently does the halfword swap when CONFIG_AP700X_16_BIT_SMC
> is set. This explains why Havard said it's wrong to use readl on
> internal deviceson avr32, but unfortunately that rule conflicts with how
> we define the accessors on ARM.
I already thought the 16-bit swap might be related to the 16-bit SMC
configuration. SMC will fetch each u32 word in 2 different 16-bit banks
of SDRAM.
In a meanwhile I tried dw_dmac using iowrite32be/ioread32be, and it worked
equally well! Which isn't surprising because for AVR32 they were defined as:
#define iowrite32be(v,p) __raw_writel(v, p)
#define ioread32be(p) ((unsigned int)__raw_readl(p))
The 'relaxed' versions won't work because:
#define readl_relaxed readl
The object code confirms what was expected:
u32 val = ioread32be (((unsigned*)0x100)); /* Same as __raw_readl */
ld.w r8,pc[256]
iowrite32be (val, ((unsigned*)0x104)); /* same as __raw_writel */
st.w pc[260],r8
val = readl (((unsigned*)0x108)); /* __raw_readl + swahb32 */
ld.w r8,pc[264]
lsl r9,r8,0x10 /* 16-bit swap */
or r9,r9,r8>>0x10
writel (val, ((unsigned*)0x10C)); /* swahb32 + __raw_writel */
lsl r8,r9,0x10 /* 16-bit swap */
or r8,r8,r9>>0x10
st.w pc[268],r8
Hein
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
