* Andi Kleen <[EMAIL PROTECTED]> wrote:
> - if (ioremap_change_attr(vaddr, size, mode) < 0) {
> + /* Fix up the direct mapping for the new cache attributes */
> + err = ioremap_change_attr((unsigned long)__va(phys_addr),
> + size + offset, mode);
Ugh. This would break the 32-bit kernel - if any phys_addr larger than
1GB is passed in (which is the common case on 32-bit) then we'll start
changing the attributes of random (most likely user-space) pages!
That is because on 32-bit __va() does this:
#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET))
where on 32-bit 3GB:1GB split PAGE_OFFSET is defined to 0xc0000000.
So if a driver passes in the physical address of a PCI device with a BAR
at 0xe1000000 somewhere in the PCI aperture, we'll get
0xe1000000+0xc0000000 == 0x91000000 - right in the middle of user-space.
Changing attributes there is very wrong. (it could even crash the kernel
in certain circumstances.)
Have you tried to boot this patch on 32-bit? There are a couple of new
safety nets in the cpa code that would/should trigger very visibly -
such as the warning here:
if (!pte_val(old_pte)) {
printk(KERN_WARNING "CPA: called for zero pte. "
"vaddr = %lx cpa->vaddr = %lx\n", address,
cpa->vaddr);
WARN_ON(1);
return -EINVAL;
}
(these are already there in -git)
Please have a look at how we solved the "secondary alias" 64-bit problem
in x86.git#mm and please resend against x86.git#mm if you still think
something is missing. Thanks,
Ingo
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