RE: [PATCH v4 3/5] iommu/x86: Add architectural MSI reserved region helper

[Michael Kelley]

From: Yu Zhang <zhang...@linux.microsoft.com> Sent: Friday, August 21, 2026 
6:27 AM
> 
> Intel and AMD IOMMU drivers both reserve the x86 architectural MSI
> address window from normal IOVA mappings, but each open-codes the range
> and its allocation attributes.
> 
> Add iommu_alloc_resv_x86_msi_region() to encapsulate those details, and
> convert the Intel and AMD drivers to use it.
> 
> Signed-off-by: Yu Zhang <zhang...@linux.microsoft.com>
> ---
>  arch/x86/include/asm/iommu.h | 14 ++++++++++++++
>  drivers/iommu/amd/iommu.c    |  6 +-----
>  drivers/iommu/intel/iommu.c  |  6 +-----
>  3 files changed, 16 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h
> index 3be2451e7bc8..6404f4fbeae8 100644
> --- a/arch/x86/include/asm/iommu.h
> +++ b/arch/x86/include/asm/iommu.h
> @@ -4,6 +4,11 @@
> 
>  #include <linux/acpi.h>
> 
> +#ifdef CONFIG_IOMMU_API
> +#include <linux/iommu.h>
> +#include <linux/sizes.h>
> +#endif
> +
>  #include <asm/e820/api.h>
> 
>  extern int force_iommu, no_iommu;
> @@ -21,6 +26,15 @@ extern bool x86_swiotlb_enable;
>  /* 10 seconds */
>  #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000)
> 
> +#ifdef CONFIG_IOMMU_API
> +static inline struct iommu_resv_region *
> +iommu_alloc_resv_x86_msi_region(void)
> +{
> +     return iommu_alloc_resv_region(0xfee00000, SZ_1M, 0,
> +                                    IOMMU_RESV_MSI, GFP_KERNEL);
> +}
> +#endif
> +
>  static inline int __init
>  arch_rmrr_sanity_check(struct acpi_dmar_reserved_memory *rmrr)
>  {
> diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
> index 4dc306a4b5c6..b9bbd9aa99a8 100644
> --- a/drivers/iommu/amd/iommu.c
> +++ b/drivers/iommu/amd/iommu.c
> @@ -50,8 +50,6 @@
>  #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
> 
>  /* Reserved IOVA ranges */
> -#define MSI_RANGE_START              (0xfee00000)
> -#define MSI_RANGE_END                (0xfeefffff)
>  #define HT_RANGE_START               (0xfd00000000ULL)
>  #define HT_RANGE_END         (0xffffffffffULL)
> 
> @@ -3140,9 +3138,7 @@ static void amd_iommu_get_resv_regions(struct device 
> *dev,
>               list_add_tail(&region->list, head);
>       }
> 
> -     region = iommu_alloc_resv_region(MSI_RANGE_START,
> -                                      MSI_RANGE_END - MSI_RANGE_START + 1,
> -                                      0, IOMMU_RESV_MSI, GFP_KERNEL);
> +     region = iommu_alloc_resv_x86_msi_region();
>       if (!region)
>               return;
>       list_add_tail(&region->list, head);
> diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
> index 2e3b3ab216f8..c4de4bbcb065 100644
> --- a/drivers/iommu/intel/iommu.c
> +++ b/drivers/iommu/intel/iommu.c
> @@ -39,8 +39,6 @@
>  #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
>  #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 
> 0x3a3e)
> 
> -#define IOAPIC_RANGE_START   (0xfee00000)
> -#define IOAPIC_RANGE_END     (0xfeefffff)
>  #define IOVA_START_ADDR              (0x1000)
> 
>  #define DEFAULT_DOMAIN_ADDRESS_WIDTH 57
> @@ -3459,9 +3457,7 @@ static void intel_iommu_get_resv_regions(struct device 
> *device,
>       }
>  #endif /* CONFIG_INTEL_IOMMU_FLOPPY_WA */
> 
> -     reg = iommu_alloc_resv_region(IOAPIC_RANGE_START,
> -                                   IOAPIC_RANGE_END - IOAPIC_RANGE_START + 1,
> -                                   0, IOMMU_RESV_MSI, GFP_KERNEL);
> +     reg = iommu_alloc_resv_x86_msi_region();
>       if (!reg)
>               return;
>       list_add_tail(&reg->list, head);
> --
> 2.52.0
> 

Reviewed-by: Michael Kelley <mhkli...@outlook.com>