On Mon, Aug 03, 2026 at 11:56:50PM +0800, Mark Brown wrote:
> As per DDI 0487 R_WTXBY we need to manage PSTATE.EXLOCK when entering an
> exception, when the exception is entered from a lower EL the bit is cleared
> while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN.
> Implement this behaviour in enter_exception64().
...
> +static unsigned long compute_exlock(struct kvm_vcpu *vcpu,
> + unsigned long mode,
> + unsigned long target_mode)
> +{
> + u64 gcscr;
> +
> + if (!kvm_has_gcs(kern_hyp_va(vcpu->kvm)))
> + return 0;
> +
> + /* GCS can't be enabled for 32 bit */
> + if (mode & PSR_MODE32_BIT)
> + return 0;
> +
> + /* When taking an exception to a higher EL EXLOCK is cleared. */
> + if ((mode | PSR_MODE_THREAD_BIT) != target_mode)
> + return 0;
Reviewed-by: Yuan Yao <[email protected]>
> +
> + /*
> + * When taking an exception to the same EL EXLOCK is set to
> + * the effective value of GCSR_ELx.EXLOCKEN.
> + */
> + if (is_hyp_ctxt(vcpu))
> + gcscr = __vcpu_read_sys_reg(vcpu, GCSCR_EL2);
> + else
> + gcscr = __vcpu_read_sys_reg(vcpu, GCSCR_EL1);
> +
> + if (gcscr & GCSCR_ELx_EXLOCKEN)
> + return PSR_EXLOCK_BIT;
> +
> + return 0;
> +}
> +
> /*
> * This performs the exception entry at a given EL (@target_mode), stashing
> PC
> * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTATE.
> @@ -154,6 +186,11 @@ static void enter_exception64(struct kvm_vcpu *vcpu,
> unsigned long target_mode,
> // PSTATE.BTYPE is set to zero upon any exception to AArch64
> // See ARM DDI 0487E.a, pages D1-2293 to D1-2294.
>
> + // PSTATE.EXLOCK is set to 0 upon any exception to a higher
> + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same
> + // exception level. See ARM DDI 0487 R_WTXBY.
> + new |= compute_exlock(vcpu, mode, target_mode);
> +
> new |= PSR_D_BIT;
> new |= PSR_A_BIT;
> new |= PSR_I_BIT;
>
> --
> 2.47.3
>
