On Mon, Aug 03, 2026 at 11:56:48PM +0800, Mark Brown wrote:
> GCS introduces a number of system registers, on systems with GCS we need
> to context switch them and expose them to VMMs to allow guests to use
> GCS.
>
> In order to allow guests to use GCS we also need to configure
> HCRX_EL2.GCSEn, if this is not set GCS instructions will be noops and
> CHKFEAT will report GCS as disabled.
>
> Signed-off-by: Mark Brown <[email protected]>
> ---
> arch/arm64/include/asm/kvm_emulate.h | 3 +++
> arch/arm64/include/asm/kvm_host.h | 14 ++++++++++
> arch/arm64/include/asm/vncr_mapping.h | 2 ++
> arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 31 ++++++++++++++++++++++
> arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 10 +++++++
> arch/arm64/kvm/sys_regs.c | 42
> ++++++++++++++++++++++++++++++
> 6 files changed, 102 insertions(+)
...
> --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
> +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
> @@ -17,6 +17,7 @@
> #include <asm/kvm_mmu.h>
>
> static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt);
> +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt);
>
> static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt)
> {
> @@ -67,6 +68,11 @@ static inline void __sysreg_save_user_state(struct
> kvm_cpu_context *ctxt)
> {
> ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0);
> ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0);
> +
> + if (ctxt_has_gcs(ctxt)) {
> + ctxt_sys_reg(ctxt, GCSPR_EL0) = read_sysreg_s(SYS_GCSPR_EL0);
> + ctxt_sys_reg(ctxt, GCSCRE0_EL1) =
> read_sysreg_s(SYS_GCSCRE0_EL1);
> + }
> }
>
> static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt)
> @@ -131,6 +137,17 @@ static inline bool ctxt_has_sctlr2(struct
> kvm_cpu_context *ctxt)
> return kvm_has_sctlr2(kern_hyp_va(vcpu->kvm));
> }
>
> +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt)
> +{
> + struct kvm_vcpu *vcpu;
> +
> + if (!cpus_have_final_cap(ARM64_HAS_GCS))
> + return false;
> +
> + vcpu = ctxt_to_vcpu(ctxt);
> + return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64PFR1_EL1, GCS, IMP);
> +}
> +
> static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
> {
> ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR);
> @@ -144,6 +161,10 @@ static inline void __sysreg_save_el1_state(struct
> kvm_cpu_context *ctxt)
> if (ctxt_has_s1pie(ctxt)) {
> ctxt_sys_reg(ctxt, PIR_EL1) =
> read_sysreg_el1(SYS_PIR);
> ctxt_sys_reg(ctxt, PIRE0_EL1) =
> read_sysreg_el1(SYS_PIRE0);
> + if (ctxt_has_gcs(ctxt)) {
> + ctxt_sys_reg(ctxt, GCSPR_EL1) =
> read_sysreg_el1(SYS_GCSPR);
> + ctxt_sys_reg(ctxt, GCSCR_EL1) =
> read_sysreg_el1(SYS_GCSCR);
> + }
> }
>
> if (ctxt_has_s1poe(ctxt))
> @@ -206,6 +227,11 @@ static inline void __sysreg_restore_user_state(struct
> kvm_cpu_context *ctxt)
> {
> write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0);
> write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0);
> + if (ctxt_has_gcs(ctxt)) {
> + write_sysreg_s(ctxt_sys_reg(ctxt, GCSPR_EL0), SYS_GCSPR_EL0);
> + write_sysreg_s(ctxt_sys_reg(ctxt, GCSCRE0_EL1),
> + SYS_GCSCRE0_EL1);
> + }
> }
>
> static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt,
> @@ -239,6 +265,11 @@ static inline void __sysreg_restore_el1_state(struct
> kvm_cpu_context *ctxt,
> if (ctxt_has_s1pie(ctxt)) {
> write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1),
> SYS_PIR);
> write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1),
> SYS_PIRE0);
> +
> + if (ctxt_has_gcs(ctxt)) {
> + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSPR_EL1),
> SYS_GCSPR);
> + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSCR_EL1),
> SYS_GCSCR);
> + }
> }
>
> if (ctxt_has_s1poe(ctxt))
> diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
> b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
> index be685b63e8cf..2431c18f5792 100644
> --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
> +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
> @@ -61,6 +61,9 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vcpu)
>
> if (ctxt_has_s1poe(&vcpu->arch.ctxt))
> __vcpu_assign_sys_reg(vcpu, POR_EL2,
> read_sysreg_el1(SYS_POR));
> +
> + if (ctxt_has_gcs(&vcpu->arch.ctxt))
> + __vcpu_assign_sys_reg(vcpu, GCSCR_EL2,
> read_sysreg_el1(SYS_GCSCR));
> }
>
> /*
> @@ -77,6 +80,8 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vcpu)
> __vcpu_assign_sys_reg(vcpu, SP_EL2, read_sysreg(sp_el1));
> __vcpu_assign_sys_reg(vcpu, ELR_EL2, read_sysreg_el1(SYS_ELR));
> __vcpu_assign_sys_reg(vcpu, SPSR_EL2, read_sysreg_el1(SYS_SPSR));
> + if (ctxt_has_gcs(&vcpu->arch.ctxt))
> + __vcpu_assign_sys_reg(vcpu, GCSPR_EL2,
> read_sysreg_el1(SYS_GCSPR));
>
> if (ctxt_has_sctlr2(&vcpu->arch.ctxt))
> __vcpu_assign_sys_reg(vcpu, SCTLR2_EL2,
> read_sysreg_el1(SYS_SCTLR2));
> @@ -133,6 +138,11 @@ static void __sysreg_restore_vel2_state(struct kvm_vcpu
> *vcpu)
>
> if (ctxt_has_s1poe(&vcpu->arch.ctxt))
> write_sysreg_el1(__vcpu_sys_reg(vcpu, POR_EL2),
> SYS_POR);
> +
> + if (ctxt_has_gcs(&vcpu->arch.ctxt)) {
> + write_sysreg_el1(__vcpu_sys_reg(vcpu, GCSCR_EL2),
> SYS_GCSCR);
> + write_sysreg_el1(__vcpu_sys_reg(vcpu, GCSPR_EL2),
> SYS_GCSPR);
> + }
Hi Mark,
Looks the s1pie checking for GCS vEL2 context switch is
necessary yet IIUC, KVM does vEL2 context switch for nested
L1's EL2, it should follow same rule as non-nested L1's EL1
context switch.
> }
>
> write_sysreg_el1(__vcpu_sys_reg(vcpu, ESR_EL2), SYS_ESR);
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 5d5c579d4579..d18ada283809 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -109,6 +109,10 @@ static enum sr_loc_attr locate_direct_register(const
> struct kvm_vcpu *vcpu,
> case PIR_EL1:
> case PIRE0_EL1:
> case POR_EL1:
> + case GCSCRE0_EL1:
> + case GCSPR_EL0:
> + case GCSCR_EL1:
> + case GCSPR_EL1:
> case ESR_EL1:
> case AFSR0_EL1:
> case AFSR1_EL1:
> @@ -200,6 +204,8 @@ static void locate_register(const struct kvm_vcpu *vcpu,
> enum vcpu_sysreg reg,
> MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL );
> MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL );
> MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL );
> + MAPPED_EL2_SYSREG(GCSCR_EL2, GCSCR_EL1, NULL );
> + MAPPED_EL2_SYSREG(GCSPR_EL2, GCSPR_EL1, NULL );
> MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL );
> MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL );
> MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL );
> @@ -228,6 +234,10 @@ static u64 read_sr_from_cpu(enum vcpu_sysreg reg)
> case TCR2_EL1: val = read_sysreg_s(SYS_TCR2_EL12); break;
> case PIR_EL1: val = read_sysreg_s(SYS_PIR_EL12); break;
> case PIRE0_EL1: val = read_sysreg_s(SYS_PIRE0_EL12); break;
> + case GCSPR_EL0: val = read_sysreg_s(SYS_GCSPR_EL0); break;
> + case GCSCRE0_EL1: val = read_sysreg_s(SYS_GCSCRE0_EL1); break;
> + case GCSCR_EL1: val = read_sysreg_s(SYS_GCSCR_EL12); break;
> + case GCSPR_EL1: val = read_sysreg_s(SYS_GCSPR_EL12); break;
> case POR_EL1: val = read_sysreg_s(SYS_POR_EL12); break;
> case ESR_EL1: val = read_sysreg_s(SYS_ESR_EL12); break;
> case AFSR0_EL1: val = read_sysreg_s(SYS_AFSR0_EL12); break;
> @@ -267,6 +277,10 @@ static void write_sr_to_cpu(enum vcpu_sysreg reg, u64
> val)
> case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break;
> case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break;
> case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break;
> + case GCSCRE0_EL1: write_sysreg_s(val, SYS_GCSCRE0_EL1); break;
> + case GCSPR_EL0: write_sysreg_s(val, SYS_GCSPR_EL0); break;
> + case GCSCR_EL1: write_sysreg_s(val, SYS_GCSCR_EL12); break;
> + case GCSPR_EL1: write_sysreg_s(val, SYS_GCSPR_EL12); break;
> case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
> case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
> case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
> @@ -2995,6 +3009,21 @@ static unsigned int cnthv_visibility(const struct
> kvm_vcpu *vcpu,
> return REG_HIDDEN;
> }
>
> +static unsigned int gcs_visibility(const struct kvm_vcpu *vcpu,
> + const struct sys_reg_desc *r)
> +{
> + if (kvm_has_gcs(vcpu->kvm))
> + return 0;
> +
> + return REG_HIDDEN;
> +}
> +
> +static unsigned int gcs_el2_visibility(const struct kvm_vcpu *vcpu,
> + const struct sys_reg_desc *rd)
> +{
> + return __el2_visibility(vcpu, rd, gcs_visibility);
> +}
> +
> static bool access_mdcr(struct kvm_vcpu *vcpu,
> struct sys_reg_params *p,
> const struct sys_reg_desc *r)
> @@ -3399,6 +3428,13 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> PTRAUTH_KEY(APDB),
> PTRAUTH_KEY(APGA),
>
> + { SYS_DESC(SYS_GCSCR_EL1), NULL, reset_val, GCSCR_EL1, 0,
> + .visibility = gcs_visibility },
> + { SYS_DESC(SYS_GCSPR_EL1), NULL, reset_unknown, GCSPR_EL1,
> + .visibility = gcs_visibility },
> + { SYS_DESC(SYS_GCSCRE0_EL1), NULL, reset_val, GCSCRE0_EL1, 0,
> + .visibility = gcs_visibility },
> +
> { SYS_DESC(SYS_SPSR_EL1), access_spsr},
> { SYS_DESC(SYS_ELR_EL1), access_elr},
>
> @@ -3523,6 +3559,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> CTR_EL0_DminLine_MASK |
> CTR_EL0_L1Ip_MASK |
> CTR_EL0_IminLine_MASK),
> + { SYS_DESC(SYS_GCSPR_EL0), NULL, reset_unknown, GCSPR_EL0,
> + .visibility = gcs_visibility },
> { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility =
> sme_visibility },
> { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility =
> fp8_visibility },
>
> @@ -3764,6 +3802,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0,
> vncr_el2_visibility),
>
> + EL2_REG_FILTERED(GCSCR_EL2, access_rw, reset_val, 0,
> + gcs_el2_visibility),
> + EL2_REG_FILTERED(GCSPR_EL2, access_rw, reset_val, 0,
> + gcs_el2_visibility),
> { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 },
> EL2_REG_VNCR_FILT(HDFGRTR2_EL2, fgt2_visibility),
> EL2_REG_VNCR_FILT(HDFGWTR2_EL2, fgt2_visibility),
>
> --
> 2.47.3
>
