On Wed, Jul 22, 2026 at 01:02:40AM +0000, Esteban Urrutia wrote:
> On 7/21/26 8:35 PM, Dmitry Baryshkov wrote:
> > Quoting commit b5383dbae381 ("disp: msm: dp: add pll params table for
> > 4nm PHY pll settings") from the SDE driver:
> >
> > Because of changes to ref clock frequency, few of the pll
> > reg values are different for kalama compared to palima.
> > This change differentiates between these two 4nm versions,
> > based on pll revision and also introduces a pll reg table
> > to differentiate the values.
> >> So, I assume, that v1 vs v1.1 is a clumsy downstream way to specify the
> > ref clock differences (which affect those tables).
>
> This does not seem to be the case...
> When HBR2 is used over a direct Type-C to Type-C DP Alt Mode connection,
> link training fails when v1.1 tables are used instead:
Yes, because the platform has different refclock.
>
> Jul 21 20:56:39 esteuwu-phone kernel: [drm:msm_dp_ctrl_link_train_1_2 [msm]]
> *ERROR* max v_level reached
> Jul 21 20:56:39 esteuwu-phone kernel: [drm:msm_dp_ctrl_link_train_1_2 [msm]]
> *ERROR* link training #1 on phy 0 failed. ret=-11
> Jul 21 20:56:39 esteuwu-phone kernel: [drm:msm_dp_ctrl_setup_main_link [msm]]
> *ERROR* link training on sink failed. ret=-11
> Jul 21 20:56:39 esteuwu-phone kernel: [drm:msm_dp_bridge_atomic_enable [msm]]
> *ERROR* Failed link training (rc=-104)
> Jul 21 20:56:39 esteuwu-phone kernel:
> [drm:dpu_encoder_phys_vid_wait_for_commit_done:545] [dpu error]vblank
> timeout: a0821300
> Jul 21 20:56:39 esteuwu-phone kernel: [drm:dpu_kms_wait_for_commit_done:527]
> [dpu error]wait for commit done returned -110
> Jul 21 20:56:39 esteuwu-phone kernel:
> [drm:dpu_encoder_frame_done_timeout:2731] [dpu error]enc37 frame done timeout
>
> > I'd suggest adding the comments about 4nm-v1 vs 4nm-v1.1 rather than
> > renaming the structs.
> Regards,
> Esteban
>
--
With best wishes
Dmitry
