This is more idiomatic and it does not really make sense for this
code to implement a own TLB flushing variant.
The control registers will be read/written a few times more, but
that should not really matter for this code.
v1->v2: Remove unused variable to fix warning
Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
---
arch/x86/kernel/cpu/mtrr/generic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Index: linux/arch/x86/kernel/cpu/mtrr/generic.c
===================================================================
--- linux.orig/arch/x86/kernel/cpu/mtrr/generic.c
+++ linux/arch/x86/kernel/cpu/mtrr/generic.c
@@ -324,7 +324,6 @@ static unsigned long set_mtrr_state(void
}
-static unsigned long cr4 = 0;
static DEFINE_SPINLOCK(set_atomicity_lock);
/*
@@ -349,14 +348,8 @@ static void prepare_set(void) __acquires
write_cr0(cr0);
wbinvd();
- /* Save value of CR4 and clear Page Global Enable (bit 7) */
- if ( cpu_has_pge ) {
- cr4 = read_cr4();
- write_cr4(cr4 & ~X86_CR4_PGE);
- }
-
- /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
- __flush_tlb();
+ /* Flush all TLBs */
+ __flush_tlb_all();
/* Save MTRR state */
rdmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
@@ -368,7 +361,7 @@ static void prepare_set(void) __acquires
static void post_set(void) __releases(set_atomicity_lock)
{
/* Flush TLBs (no need to flush caches - they are disabled) */
- __flush_tlb();
+ __flush_tlb_all();
/* Intel (P6) standard MTRRs */
mtrr_wrmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
@@ -376,9 +369,9 @@ static void post_set(void) __releases(se
/* Enable caches */
write_cr0(read_cr0() & 0xbfffffff);
- /* Restore value of CR4 */
- if ( cpu_has_pge )
- write_cr4(cr4);
+ /* Flush TLBs again to handle prefetches etc. */
+ __flush_tlb_all();
+
spin_unlock(&set_atomicity_lock);
}
--
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